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基本信息

書名：FPGA芯片架構設計與實現

定價：56.00元

作者：餘樂

齣版社：電子工業齣版社

齣版日期：2017-07-01

ISBN：9787121306105

字數：

頁碼：

版次：1

裝幀：平裝-膠訂

開本：16開

商品重量：0.4kg

編輯推薦

內容提要

可編程通用邏輯門陣列芯片簡稱FPGA，與CPU，DSP並列為三大通用數字處理芯片，廣泛應用於通信、航空航天、醫療、國防軍工以及安防視頻監控等領域。通過本書的學習，讀者可以全麵瞭解一顆FPGA芯片從設計、驗證到流片的開發過程。 本書共分10章，采取“總—分”的編排方式。章從架構的總體設計入題對FPGA進行介紹。第2~10章，分彆對其中的各個重要模塊逐一介紹，包括：時鍾網絡、電源/地綫網絡和漏電流、可編程邏輯單元、可編程I/O模塊、DDR存儲器接口、數字延時鎖定環、連綫連接盒、互連綫段長度分布以及配置模塊。 本書適閤從事集成電路設計的工程師、微電子專業高年級研究生以及從事微電子專業教學研究的教師和科研人員閱讀。本書還可以作為高等院校教授集成電路設計的輔助資料。

目錄

章 FPGA 架構總體設計 ········································································· 1
1.1 FPGA 芯片研製流程·········································································· 1
1.2 FPGA 架構設計流程·········································································· 7
1.3 FPGA 規模和資源劃分 ····································································· 17
1.4 FPGA 中功能模塊劃分 ····································································· 20
本章參考文獻 ······················································································ 26
第2 章 FPGA 中時鍾網絡 ·········································································· 30
2.1 簡介 ···························································································· 30
2.2 FPGA CDN 建模 ············································································· 33
2.3 時鍾網絡設計方法 ·········································································· 43
2.4 時鍾網絡的靈活性 ·········································································· 48
2.5 路由級聯 ······················································································ 51
2.6 仿真實驗 ······················································································ 55
2.7 時鍾網絡熱學建模 ·········································································· 61
2.8 仿真實驗 ······················································································ 62
本章參考文獻 ······················································································ 66
第3 章 FPGA 中電源/地綫網絡和漏電流 ······················································· 68
3.1 電源/地綫網絡 ··············································································· 68
3.2 IR-DROP 分析與優化 ········································································ 71
3.3 漏電流組成 ··················································································· 73
3.4 降低漏電流的方法 ·········································································· 74
3.5 基於VIA 分布的IR-DROP 分析 ··························································· 77
3.6 仿真實驗 ······················································································ 81
3.7 不均勻測試點的IR-DROP 求解 ··························································· 87
3.8 FPGA 電源網絡IR-DROP 分析 ···························································· 89
本章參考文獻 ······················································································ 94
第4 章 FPGA 中可編程邏輯單元 ································································· 98
4.1 基於多路選擇器的邏輯單元 ······························································ 98
4.2 基於四輸入LUT 的可編程邏輯單元的設計 ·········································· 102
4.3 LUT 的模型與實現 ········································································ 103
4.4 LUT 的輸入數目K 的確定 ······························································· 106
4.5 進位邏輯 ····················································································· 109
4.6 基於查找錶結構的FPGA 的不足 ······················································· 115
4.7 AIC 結構邏輯簇 ············································································ 117
4.8 基於AIC 結構FPGA 的邏輯簇 ························································· 120
4.9 麵嚮AIC 的映射工具及結構評估平颱 ················································ 124
4.10 結構特徵匹配的AIC 簇互連優化 ···················································· 125
4.11 仿真分析和比較 ·········································································· 131
本章參考文獻 ····················································································· 133
第5 章 FPGA 中可編程I/O 模塊 ································································· 136
5.1 可編程I/O 係統結構 ······································································ 136
5.2 IOE 中的可編程輸入緩衝器設計 ······················································· 138
5.3 IOE 中的可編程輸齣緩衝器設計 ······················································· 144
5.4 可編程I/O 的後端版圖設計······························································ 156
5.5 高可靠I/O 模塊的後端版圖與測試 ····················································· 166
5.6 可編程I/O 的供電策略 ··································································· 172
5.7 全芯片IO 的ESD 技術 ····················································

作者介紹

申請人於2009年3月至2012年8月在中科院電子所可編程芯片與係統研究室攻讀博士學位，從事下一代SOC FPGA的關鍵集成技術研究。博士課題來源於中科院/國傢外專局的創新團隊國際閤作夥伴計劃'片上可編程係統前沿技術研究”。博士畢業獲微電子與固體電子學博士學位。同年，以申請人博士論文為基礎，幫助實驗室申請瞭國傢自然科學基金麵上項目'基於TSV互連的三維FPGA架構及關鍵技術研究”。2012年博士畢業後，選擇留所繼續從事博士後研究工作，並作為國自基金項目的實際負責人，管理項目的整體推進，指導學生完成瞭2篇論文的投稿。博士後期間，參與瞭兩款FPGA芯片的研製工作，分彆是0.13um 百萬門級FPGA（中科院重點方嚮性項目）和40nm FPGA-ip核（國傢重大專項）。2015年博士後齣站，齣站報告'FPGA時鍾分布網絡研究”從延時、麵積、功耗、靈活性以及熱性能等多方麵，對FPGA的關鍵架構技術進行瞭研究。

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